Clock and reset

The ECPIX-5 development offers a wide variety of clock inputs to accomodate specific usages.

Clock sources

100Mhz system clock

FPGA pin: K23

100Mhz SERDES reference clock

FPGA pins: AF12 (P) / AF13 (N)

26Mhz SD clock

FPGA pin: N22

Extra oscillator source

An unpopulated spot (X4, near the FPGA) lets you use the oscillator of your choice.

FPGA pin: H26

Reset circuitry

Reset buttons

ECPIX-5 has two reset buttons:

  • GSRN (Global Reset): Performs a hardware reset operation on the ECP5

  • System Reset: Performs a hardware reset of the peripherals (FTDI, HDMI, ULPI, Ethernet, DDR3) and a soft reset of the ECP5 (FPGA pin: N5). This System Reset can be triggered by the FPGA itself (FPGA pin: M6)

The system reset signal is generated by a MAX6420 reset generator. It lasts a few milliseconds and ensure a proper bounce-less reset of the system.

FPGA-controlled reset

All the peripherals (FTDI, HDMI, ULPI, Ethernet PHY) can be independantly reset by the FPGA.

Peripheral

FPGA reset pin

FTDI debug interface

P23

HDMI encoder

N6

USB PHY

E23

Ethernet PHY

C13